The present invention relates in general to semiconductor products. More particularly, it relates to via structures used in semiconductor products.
The escalating requirements for high density and performance associated with ultra large scale integration (ULSI) semiconductor device wiring are difficult to satisfy in terms of providing sub-micro-sized, low resistance-capacitance (RC) metallization patterns. This is particularly applicable when the sub-micro-features, such as vias, contact areas, lines, trenches, and other shaped openings or recesses have high aspect ratios (depth-to-width) due to miniaturization.
Copper (Cu) or copper-based alloy has been used as the major material for semiconductor wiring to replace aluminum (Al), due to the low resistance and high melting point provided by Cu. Cu, however, lacks excellent properties that Al has. For example, Cu cannot form a dense protective layer such as Al2O3, has bad adhesive strength to SiO2, and is difficult to dry-etch. In addition, its diffusion coefficient in silicon is approximately 106 times larger than that of Al, and it is known that Cu diffused into the silicon forms a deep level in a band gap. Furthermore, copper's diffusion coefficient in SiO2 is known to be large, which decreases the ability of SiO2 to insulate between Cu lines. As a result of copper's large diffusion coefficient in silicon and SiO2, the reliability of the semiconductor device is reduced. Accordingly, to ensure the reliability of the device, a diffusion barrier layer capable of blocking Cu from rapidly diffusing into the silicon or SiO2 is required.
FIG. 1 shows the general concept of a dual damascene process for manufacturing Cu lines with a barrier layer. An inter-metal dielectric (IMD) or an inter-layer dielectric (ILD) 100 is patterned through lithographic and etch processes to define a trench and a via hole. A diffusion barrier layer and a seed layer are then deposited to coat the trench, the via hole, and the top surface of the dielectric layer. Through the assistance from the seed layer, Cu is then plated on the entire surface to fill the trench and the via hole. Chemical mechanical planarization can be used to remove the excessive copper on the top surface of the dielectric layer. Copper in the trench and the via hole respectively provide lateral and vertical electronic connections.
The general requirements for barrier layers include:
step coverage on high aspect ratio via holes and trenches;
low thin film resistivity;
adhesion to the IMD or ILD;
adhesion to Cu;
stability at all process temperatures;
compatibility to the IMD or ILD;
compatibility to CMP process; and
resistance to Cu diffusion.
In view of these requirements, Ta and/or TaN thin films deposited by a sputtering process are currently being used as the diffusion barrier layer for Cu. Challenge for forming a better diffusion layer, however, still remains.